The XAUI (Ten Gigabit Attachment Unit Interface) is a 10 bps attachment interface unit for delivering 10 Gbps Ethernet speeds for chip-to-chip, board to board, and interbox communications. The XAUI spec defines four 3.125-Gbps streams for a total of 12.5-bps, which, taking into account 8 B/10 B encoding overhead, supports a 10 gigabit throughput with a maximum skew of 40 UI (unit interval).
In a typical environment, 10-Gbps parallel data received on a wide parallel bus is serialized, 8 b/10 b encoded, and transmitted on the four 3.125-Gbps XAUI lanes. At the receiver the serial data is reformatted in parallel form for transmission on a parallel bus. If the routing of the four XAUI lanes is not closely matched then the data received on one lane will be skewed relative to data received on the other lanes. The XAUI spec provides for automatic deskewing of the lanes to eliminate the requirement of closely matching the routes for each lane. Skew is introduced between lanes by both active and passive elements of a XAUI link. The IEEE 802.3ae PCS deskew function compensates for all lane-to-lane skew observed at the receiver.
XAUI is a self-timed interface having the timing clock embedded within the data. The data stream includes an alignment character (/A/) that is detected by a synchronization unit and used to align the data on the different lanes to deskew the data. Typically, data from each XAUI lane is buffered by a FIFO. The repetition of the alignment character (/A/) on each serial channel allows the FIFOs to remove or add the required phase delay to align the /A/ on each lane thereby deskewing the data on each of the four XAUI lanes.
This alignment process is schematically depicted in FIGS. 1A and B. In FIG. 1A the received data on each of the four XAUI lanes are skewed relative to each other. In FIG. 2B the data has been realigned to that the /A/ character in each lane is in the same column.
For point to point connections, all the 4 serial lanes will end in the same chip, so that only a single PCS (Physical Coding Layer) deskew state machine, as defined in IEEE P802.3ae figure 48-8, is required to deskew the 4 XAUI lanes. This specification is hereby incorporated by reference for all purposes.
Implementation of 10 Gbps Ethernet requires NxN switch fabrics capable of switching 10 Gbps data streams. However, the implementation of an NxN 10 GE switch fabric (N>=64) as a single chip ASIC is either not feasible or just too expensive with present semiconductor fabrication methods because of the large number of ports. One solution is to implement the NxN 10 GE switch fabric as 4 NxN 2.5 G chips with each chip operating on a single XAUI lane thus reducing the clock data rate on each chip by a factor of four. However, this creates the problem of deskewing 4 XAUI lanes across 4 different ASIC chips.